Privilege Level Switching and Simple Trap Implementation
Understanding VA2PA translation in sv39 three-level page tables and building minimal MVP with xv6 reference.
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Privilege Level Switching and Simple Trap Implementation
Exploring RISC-V privilege architecture for Sv39 paging, PMP configuration, and trap delegation from M-mode to S-mode.
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Brief note on implementing cyclic lists with sentinel nodes for memory allocator modification.
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Development log covering directory structure setup, printf encapsulation challenges, and LD linker issues in kernel development.
Read moreUART Manual Review and Analysis of xv6 uart.c
Detailed analysis of UART 16650 registers in xv6's uart.c implementation, covering IER, FCR, LCR configurations and their manual specifications.
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