devlog 12-21
Clarifying IP vs IE interrupt concepts in RISC-V, hardware configuration issues, and trap entry point implementation lessons.
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PTE's Confusion Issues and Problem Tracking and Handling
Addressing chicken-and-egg problems in high-address mapping, PTE allocation misconceptions, and implementing ekalloc for boot-time memory management.
Read moredevlog 12-19
Challenges in implementing high-half kernel mapping, modifying kalloc for pre/post-paging allocation strategies.
Read morePrivilege Level Switching and Simple Trap Implementation
Understanding VA2PA translation in sv39 three-level page tables and building minimal MVP with xv6 reference.
Read morePrivilege Level Switching and Simple Trap Implementation
Exploring RISC-V privilege architecture for Sv39 paging, PMP configuration, and trap delegation from M-mode to S-mode.
Read moredevlog 12-12
Brief note on implementing cyclic lists with sentinel nodes for memory allocator modification.
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