Implementation of UART interrupts
Implementing UART TX interrupts with buffer management, LSR register handling, and debugging ebreak interrupt issues.
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Implementing UART TX interrupts with buffer management, LSR register handling, and debugging ebreak interrupt issues.
Read moreImplementing CLINT timer interrupts with RISC-V privilege mode handling, mscratch usage, and interrupt delegation challenges.
Read moreClarifying IP vs IE interrupt concepts in RISC-V, hardware configuration issues, and trap entry point implementation lessons.
Read moreAddressing chicken-and-egg problems in high-address mapping, PTE allocation misconceptions, and implementing ekalloc for boot-time memory management.
Read moreChallenges in implementing high-half kernel mapping, modifying kalloc for pre/post-paging allocation strategies.
Read moreUnderstanding VA2PA translation in sv39 three-level page tables and building minimal MVP with xv6 reference.
Read moreExploring RISC-V privilege architecture for Sv39 paging, PMP configuration, and trap delegation from M-mode to S-mode.
Read moreBrief note on implementing cyclic lists with sentinel nodes for memory allocator modification.
Read moreDevelopment log covering directory structure setup, printf encapsulation challenges, and LD linker issues in kernel development.
Read moreDetailed analysis of UART 16650 registers in xv6's uart.c implementation, covering IER, FCR, LCR configurations and their manual specifications.
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