xv6 : {

define IER 1

define IER_RX_ENABLE (1<<0)

define IER_TX_ENABLE (1<<1)

}

IER(Interrupt Enable Register) : { 0000 0000 just 00h(Reset Value) subsequent defaule the last four digits are invaild.

althought IER and IER_RX_ENABLE have identical numerical values , IER defines the offset address of a register, while IER_RX_ENABLE is a mask for a specific bit within that register.

the offset for IER and other addresses are all documented in the register section.

the first one is for the data-ready interrupt that is #define IER_RX_ENABLE 1.

set the second bit to 1 to enable transmission

for other details, please refer to the UART16650 manual. }

{ the uart166500 manual does mention an IIR, but xv6 does not utilize it. }

xv6 : {

define FCR 2

define FCR_FIFO_ENABLE (1<<0)

define FCR_FIFO_CLEAR (3<<1)

}

FCR(FIFO Control register) : { 1100 0000 just C0H just like above, look up uart166500 manual to find about the function of each bit.

FIFO is enabled by default; the FCR_FIFO_ENABLE setting can be either enabled or disable.

FCR_FIFO_CLEAR is implemented by setting bits 1 and 2 to 1 perform the clear operation. }

xv6 : {

define LCR 3 // line control register

define LCR_EIGHT_BITS (3<<0)

define LCR_BAUD_LATCH (1<<7)

} Line Control Register (LCR):{ 0000 0011 just 03H set the size of a character to 8bit by setting the first two bits to 1.

and enable the read divider latch to read the baud rate. }

{ LSR is specificall designed to handle errors. }

{ Note: when LCR's eight bit setted 1, the adr(0) and adr(1) will not present RHR and THR that will present DLL and DLM }