{ today, i plan to review the RISC-V privilege architecture manual to see how to implement Sv39 paging.

the core section is introduced in Chapter 12.1.11 and subsequent chapters on sv39 pagination.

the focus should not be solely on pagination issues, but also on privilege level switching.

the privilege level is still in M mode, it needs to be switched to S mode.

however, changes to the privilege levels are scattered throughout the privilege architecture manual without detailed explanation.

it was discovered that the sections on the traps and mastatus describe how to switch privilege levels. }

{ The Physical Memory Protection chapter explains the usage of PMP, which provides instruction fetching and data access for S mode. This requires configuring the relevant pmpaddr and pmpcfg parameters, as well as carefully reviewing the manual's specifications--such as configuration of the A field within PMP.

configuer PMP. PMP will perform checks when MPP is set to S or U in mstatus. In PMP, the three permission bits R/X/W must be set

Here we intend to configuer addr0 and cfg0, setting their usable range with an upper bound of pmpaddr0 and a lower bound of 0. Below is the original text from the manual: If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y